Field of the Invention
This invention relates to a nonvolatile semiconductor memory device with a plurality of dielectric films and electrode films alternately stacked on a substrate, and a method for manufacturing the same.
Background Art
Recently, to increase the density of flash memory, a technique for multilayering cells has been developed. In this technique, dielectric films and electrode films are alternately stacked on a substrate, and then through holes are simultaneously formed therein. A charge storage layer for retaining charge is formed on the inner surface of the through holes, and a columnar semiconductor pillar is buried inside each through hole. Thus, a memory cell is formed at each intersection between the semiconductor pillar and the electrode film. Then, the uppermost electrode film is divided into a plurality of select gate lines extending in one direction, and a plurality of bit lines extending in another direction are provided above the electrode film and connected to the upper end portion of the semiconductor pillars, so that any of the semiconductor pillars can be selected. On the other hand, a diffusion region is formed in an upper portion of the substrate to serve as a source electrode connected to the lower end of the semiconductor pillars. Thus, a flash memory with memory cells three-dimensionally stacked can be fabricated (see, e.g., JP-A-2007-266143(Kokai)).
However, in such a stacked flash memory, the conductive portions are three-dimensionally arranged. Hence, the conductive portions located other than in the uppermost interconnect layer, such as the diffusion region constituting the source electrode and the electrode film constituting the select gate line and the word line, can be supplied with an electric potential only through the respective end portions thereof. Thus, if the area of the stacked flash memory is increased to increase the capacity, the aforementioned conductive portions are also upsized, unfortunately increasing the resistance. This makes it difficult to rapidly place each conductive portion at a desired potential, which results in increased time required for data write, read, and erase operation, and may cause malfunctions. On the other hand, to avoid upsizing of the conductive portions, division into a plurality of memory cell arrays may be contemplated. However, in this case, each memory cell array requires a row decoder and other circuits, which increases the chip area.